module registerFile(
    input           clock,
    input   [4:0]   Rs_address,
    input   [4:0]   Rt_address,
    input   [4:0]   Rd_address, 
    input   [31:0]  Rd_data,
    input           regWrite, 
    output  [31:0]  Rs_data, 
    output  [31:0]  Rt_data 
);

// Register file has 32 32-bit registers
reg     [31:0]  register    [0:31];

// Read Data      
assign  Rs_data = (Rs_address == 5'b0) ? 32'b0 : register[Rs_address];
assign  Rt_data = (Rt_address == 5'b0) ? 32'b0 : register[Rt_address];

// Write Data   
always @(posedge clock) begin
    if(regWrite)  register[Rd_address] <= Rd_data;
end

endmodule 
